REC 2013

Thursday, 7 February 2013

Friday, 8 February 2013

The meeting features three invited presentations about research projects and industrial applications that exploit FPGAs and reconfigurable systems.

1. FPGA-Based Smart Camera for industrial applications

Speaker: Julien Dubois
LE2I (Laboratoire d’Electronique, Informatique et Image) – CNRS, France

For the last two decades and still today, smart cameras offer innovative solutions for industrial vision applications. This kind of system associates a flexible image acquisition with high-speed processing possibilities. Many smart camera designs are based on FPGA components to obtain these two features. Indeed, the FPGA enables the CMOS sensor to be controlled and therefore to propose a configurable acquisition according to the application constraints (i.e. dynamic windowing). The configurable structure of a FPGA represents a key advantage for modifying the embedded processing (even on-the-fly using dynamic reconfiguration). Meanwhile, FPGA components offer a large number of hardware resources, such as multipliers or embedded memory blocks, which enable complex image processing to be implemented and to be performed in real-time. Designers can even consider increasing the spatial image resolution and/or the frame-rate due to the FPGA technology improvements. The new solutions on the prototyping tools as well as the modelling languages available for FPGA design should be considered. Indeed, design methods based on High-Level Synthesis (HLS) enable the time to market to be significantly reduced. Moreover, these improvements enable gains on the smart camera design to be obtained, as for instance quick HW/SW implementations or quick communication interface integrations.

After a general presentation of the smart camera structure, the Le2i laboratory’s experience on smart camera designs will be used to highlight these gains.. The high processing capacities of a FPGA component at high frame rates, with high resolution images, will be demonstrated The presentation of the impact of co-processing on the smart camera performances, followed by a description of a new data-flow formalism, which enables quick prototyping of HW/SW implementations including communication interfaces to be automatically obtained, will be proposed. Finally a configurable system supporting automatic video compression adaptation in function of event detection will be presented.

Keywords : smart camera, configurable systems, co-processing, High-Level Synthesis, communication interfaces

2. Secure computation using reconfigurable systems

Speaker: Ricardo Chaves
INESC-ID/IST, TULisbon, Portugal

With the vast expansion of electronic systems and digital information usage, an increasing demand from applications and users for secure and reliable computing environments arises. To deal with this demand, several mechanisms are being developed at different levels in computing and communications systems, namely at protocol, architectural, and algorithm levels.

An emerging new requirement to security systems is flexibility in terms of fast adaptation to new protocols, algorithms, and newly developed attacks. To provide this flexibility and adaptability while maintaining an adequate performance, the usage of reconfigurable devices, such as FPGAs, are of key importance.

Recent FGPAs have the additional advantage of enabling dynamically partial reconfiguration. However, this raises another security issue since it must be assure that whatever is being loaded into the reconfigurable device is in fact being loaded into the intended location and that once loaded it will behave as expected.

This presentation will discuss how the computation of security protocols and algorithms can be improved with the use of reconfigurable devices and how these reconfigurable devices can be securely used.

3. HDMI and MIPI Prototyping Platforms

Speaker: António Costa, Miguel Falcão
Synopsys Maia, Portugal

One of the key components of Synopsys products are microelectronics sub-systems that are acquired by most of the semiconductors top vendors for integration in their SOC. These subsystems are commonly called IPs (for Intellectual Property) and Synopsys is the worldwide lead vendor of interface IP that includes popular standards such as USB, PCIe, DDR, SATA, HDMI, MIPI, etc...

HDMI and MIPI Controllers and PHY IPs are developed at Synopsys Portugal - Porto site. The quality of Synopsys IPs is worldwide recognized and such success is due to the quality of the design, verification and test flows.

The test flow requires prototyping these protocols in Synopsys laboratories where protocol controllers are prototyped in FPGA and connected to Synopsys PHYs implemented in real foundry silicon testchip. Prototyping is the ultimate verification and proof of the quality and robustness of the IP. It assures that our customer will receive a fully functional product when integrating it in their chips The importance of FPGA-based HAPS Prototyping activities is huge due to the impact it has in the business.

FPGA-based HAPS Prototyping platforms for HDMI and MIPI IP, its usages (both technical and business-oriented), past and future challenges and solutions will be presented.

http://www.synopsys.com

Organization