REC 2013 - 9th Portuguese Meeting on Reconfigurable Systems - Program

Thursday, 7 February 2013

09:00	Registration
09:30	Opening session chair: Jorge Lobo, Manuel Gericota, Anibal T. de Almeida
09:45	Invited presentation chair: Jorge Lobo FPGA-Based Smart Camera for industrial applications Julien Dubois LE2I (Laboratoire d’Electronique, Informatique et Image) – CNRS
10:45	Coffee break
11:15	Regular session: Experimental and Educational Platforms chair: Manuel Gericota Using FPGAs to create a reconfigurable IEEE1451.0-compliant weblab infrastructure Ricardo Costa, Gustavo Alves, Mário Zenha-Rela A Remote Demonstrator for Dynamic FPGA Reconfiguration Hugo Marques, João Canas Ferreira Modular SDR Platform for Educational and Research Purposes André Faceira, Arnaldo Oliveira, Nuno Borges de Carvalho
12:30	Lunch
14:00	Invited presentation chair: José Augusto Secure computation using reconfigurable systems Ricardo Chaves INESC-ID - IST
15:00	Regular session: Communication Interfaces chair: Horácio Neto Dimensionamento de buffers para redes ponto a ponto de sistemas GALS especificados através de redes de Petri Filipe Moutinho, José Pimenta, Luís Gomes Accelerating user-space applications with FPGA cores: profiling and evaluation of the PCIe interface Adrian Matoga, Ricardo Chaves, Pedro Tomás, Nuno Roma Communication Interfaces for a New Tester of ATLAS Tile Calorimeter Front-end Electronics José Domingos Alves, José Silva, Guiomar Evans, José Soares Augusto
16:15	Coffe break
16:45	Regular session: New Approaches to Reconfigurable Systems Design chair: Luis Gomes Automatic Generation of Cellular Automata on FPGA André Costa Lima, João Canas Ferreira Computational Block Templates Using Functional Programming Models Paulo Ferreira, João Canas Ferreira, José Carlos Alves
17:35	Regular session: Multiprocessing Architectures chair: Paulo Flores Using SystemC to Model and Simulate Many-Core Architectures Ana Rita Silva, Wilson José, Horácio Neto, Mário Véstias Projecto de uma Arquitectura Massivamente Paralela para a Multiplicação de Matrizes Wilson José, Ana Rita Silva, Horácio Neto, Mário Véstias
18:25	Closing of the first day
20:00	Dinner

Friday, 8 February 2013

09:00	Regular session: Architectures for High Throughput Processing chair: Arnaldo Oliveira Hardware Accelerator for Biological Sequence Alignment using Coreworks® Processing Engine José Cabrita, Gilberto Rodrigues, Paulo Flores FPGA Based Synchronous Multi-Port SRAM Architecture for Motion Estimation Purnachand Nalluri, Luís Nero Alves, António Navarro Evaluation and integration of a DCT core with a PCI Express interface using an Avalon interconnection Sérgio Paiágua, Adrian Matoga, Pedro Tomás, Ricardo Chaves, Nuno Roma
10:15	Coffe break
10:45	Invited presentation chair: José Carlos Alves Synopsys HDMI and MIPI Prototyping Platforms António Costa, Miguel Falcão R&D Manager - Synopsys Portugal
11:45	Regular session: Dynamic Reconfiguration chair: João Canas Ferreira Reconfiguração Dinâmica Parcial de FPGA em Sistemas de Controlo José Luís Nunes, João Carlos Cunha, Raul Barbosa, Mário Zenha-Rela FPGA Implementation of Autonomous Navigation Algorithm with Dynamic Adaptation of Quality of Service José Carlos Sá, João Canas Ferreira, José Carlos Alves
12:35	Closing session
12:45	Lunch

Sponsors

Organization

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